A Digital Polar Transmitter (DPTX) architecture may provide a reduced size and a reduced power consumption when compared to a conventional analog radio transmitter architecture. For example, a DPTX architecture may include two main functional blocks. One main functional block is a Digital-to-Time Converter (DTC) that modulates a local oscillator (LO) carrier with phase information of a signal that is to be transmitted. While the other main functional block is a Digital Power Amplifier (DPA) that modulates the amplitude of the signal that is to be transmitted onto the phase-modulated LO signal, thereby generating a reconstruction of the original signal (e.g., the signal to be transmitted).
In modern technologies we aim to implement the DPTX in order to improve key performance indicators and to achieve better power consumption, efficiency and compatibility. For example, the DTC in the transmission chain has a very low jitter frequency offset generator and may be further used in the receive chain. However, technologies such as 5G cellular and Wi-Fi 11ac/11ax drive carrier frequency to higher frequencies in order to achieve higher signal bandwidth (BW). To this end, present phase modulator topologies are problematic when implemented to operate at high frequencies due to timing issues and power consumption which increase exponentially with frequency.